Universal Software Radio Peripheral (USRP) |
The usrp_sink block is used to transfer data from a Simulink model to the USRP. To get a connection to the USRP, the usrp_helper block is mandatory.
This block consumes a certain number of input streams (depending on how many daughterboards on the USRP are enabled) and sends them out to the USRP.
The usrp_sink block has "per-block" settings, displayed on the USRP tab pane, and "per-daughterboard" settings, displayed on the Side A and Side B tab panes.
Specify on which USRP board this usrp_sink block acts upon. The first USRP board is numbered 0, the second 1 etc.
Informational message stating the USB serial number of the specified USRP board. Read only.
Specifies the interpolation factor which is to be used inside the USRP to bring the baseband sample rate to 128 MSps. Some restrictions apply, depending on the choosen FPGA bitstream. If the interpolation factor could not be set when starting the simulation, check that it is inside the supported range of the FPGA. For some FPGA bitstreams, the interpolation factor must be a multiple of four.
Number of bytes to transfer across the USB bus for one sample. For usrp_sink blocks, 16 bit is the only allowed value.
Displays the effective bandwidth across the USB bus, depending on the number of enabled daughterboards/subdevices and the Sample Width. Read only.
Number of samples of one input frame of this block. This number must be calculated in a way such that the block size that goes over the USB bus is a multiple of 512 bytes. That means that the equation
Vector length * 2 * Sample Width/bytes * Number of active channels mod 512 = 0 |
must be true. The factor 2 comes from complex samples.
Displays the type of the daughterboard installed on the USRP. Read only.
Enables transmitting with this daughterboard when set to anything different from Disabled. For each daughterboard which is not disabled, one complex-valued input port or two real-valued input ports of the specified data type appear on this Simulink block.
For example, assume that the Data Type of the daughterboard on Side A is set to INT16, and that of Side B is set to SINGLE Complex. This means that input port one of this block expects a stream of real-valued frames, being the in-phase part of the signal going to daughterboard A. Input port two expects the real-valued quadrature part of the same signal. The daughterboard on side B is fed by the complex-valued stream going into port three of this block.
Displays the frequency range that is supported by this daughterboard. Read only.
Enables a frequency input port to tune the seleceted daughterboard during runtime. The port expects a real-valued and sample-based signal of datatype DOUBLE. The sample-time of the input port is defined by the usrp_sink block.
Setting the value Frequency (Hz) is still required for initialization purpose.
Enter the frequency at which the signal entering this block shall be transmitted with the USRP.
Displays the gain range supported by this dautherboard. Read only.
Enter any gain or attenuation within the gain range of the daughterboard.
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