USRP FRS Demo
Contents
Overview
This model builds an FRS transceiver. It consists of an FPGA and a GPP part. The FPGA part decimates the ADC rate of 64MHz to the 25 kHz FRS bandwidth with 2 cascaded CIC decimators on the receive side while it interpolates the 25 kHz coming from the GPP to 32 MHz on the transmit side. Though the DAC on the USRP samples with a rate of 128 MHz, DACs provide internal hardware interpolation with a factor of 4. You can simulate this model by clicking on the run button or creating a bitfile by double-clicking on the Bitfile-Generator block. The GPP side of the transceiver implements the frequency modulator while the receive side vice verca demodulates the signal and send it to the soundcard.
Model
You can open the FPGA model here
You can open the GPP model here
Screenshots
This is the model to generate the FPGA Bitstream

This is the model running on your USRP. Make sure you include the right bitstream
