Universal Software Radio Peripheral (USRP) |
The usrp_source block is used to transfer data from the USRP to a Simulink model. To get a connection to the USRP, the usrp_helper block is mandatory.
This block produces a certain number of output streams (depending on how many subdevices on the daughterboards on the USRP are enabled) by reading data from the USRP.
The usrp_source block has "per-block" settings, displayed on the USRP tab pane, and "per-subdevice" settings, displayed on the Side A - 1 through Side B - 2 tab panes.
Specify on which USRP board this usrp_source block acts upon. The first USRP board is numbered 0, the second 1 etc.
Informational message stating the USB serial number of the specified USRP board. Read only.
Specifies the decimation factor which is to be used inside the USRP to bring the ADC sample rate of 64 MSps to the baseband sample rate. Some restrictions apply, depending on the choosen FPGA bitstream. If the decimation factor could not be set when starting the simulation, check that it is inside the supported range of the FPGA. For some FPGA bitstreams, the decimation factor must be even.
Number of bytes to transfer across the USB bus for one sample. Setting this to 8 Bit yields in a higher maximum sample rate across the USB but decreases the dynamic range of the captured signal.
Displays the effective bandwidth across the USB bus, depending on the number of enabled daughterboards/subdevices and the Sample Width. Read only.
Number of samples to put into one output frame of this block. This number must be calculated in a way such that the block size that goes over the USB bus is a multiple of 512 bytes. That means that the equation
Vector length * 2 * Sample Width/bytes * Number of active channels mod 512 = 0 |
must be true. The factor 2 comes from complex samples.
Displays the type of the daughterboard installed on the USRP. Read only.
Enables receiving with this subdevice when set to anything different from Disabled. For each subdevice which is not disabled, one complex-valued output port or two real-valued output ports of the specified data type appear on this Simulink block.
For example, assume that the Data Type of the daughterboard on Side A - 1 is set to INT16, and that of Side B - 1 is set to SINGLE Complex. This means that output port one of this block produces a stream of real-valued frames, being the in-phase part of the signal from subdevice 1 on daughterboard A. Output port two produces the real-valued quadrature part of the same signal. Subdevice 1 on the daughterboard on side B produces one complex-valued stream on port three of this block.
Displays the frequency range that is supported by this daughterboard. Read only.
Enables a frequency input port to tune the seleceted daughterboard during runtime. The port expects a real-valued and sample-based signal of datatype DOUBLE. The sample-time of the input port is defined by the usrp_source block.
Setting the value Frequency (Hz) is still required for initialization purpose.
Enter the frequency at which a signal shall be captured.
Displays the gain range supported by this subdevice. Read only.
Enter any gain within the gain range of the daughterboard.
Daughterboards with multiple antenna input ports can be configured to use one specified input connnector for the signal. Setting this parameter to a value which is not available on the dautherboard usually produces an error (or has no effect at all, depending on the type of the dautherboard).
The setting I&Q (BasicRX/LFRX only) has a special meaning. The two input connectors on thoses dautherboards are usually mapped to the two subdevices of the dautherboard. If, however, both inputs are fed by the inphase and quadrature parts of the same signal, they both can be combined into one complex signal. In this case, subdevice two can not be used seperately any more. (In fact, this setting chooses subdevice three on those boards.)
The Antenna parameter is only available on the first subdevice of each daughterboard.
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