USRP FPGA Counter Demo

Contents

Overview

This model creates a two counters on the FPGA running at 250kHz. The date from the first one are transmitted on the real part and increment by one while the data from the other one are transmitted on the complex part and increment by two. You can simulate this model by clicking on the run button or creating a bitfile by double-clicking on the Bitfile-Generator block. After generating the bitfile you can test your FPGA by running testFPGACounter.mdl and selecting fpgaCounter.rbf with the Set Bitstream block

Model

You can open the FPGA model here

You can open the GPP model here

Screenshots

This is the model to generate the FPGA Bitstream

This is the model to test the Bitstream on your USRP