Bitfile_Generator

The Bitfile_Generator block is used to generate a custom bitstream for the Altera Cyclone FPGA on the USRP mainboard.

Description

Based on a Simulink model, the Bitfile Generator first produces a HDL-file using the Simulink HDL Libraries and Coder (see Simulink HDL Coder help for more detailed information). Afterwards, the place&route process is performed by the Altera Quartus II Software. The flow graph below shows the whole process. The generated bitfile (*.rbf) can be set using the Set Bitstream block (see help usrp_helper).

Bitfile Generator Build Process

Things to keep in mind


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